In order to digitize a sum of signals there are basically two options available: either all signals are digitized with different analog-to-digital converters (ADCs) and combined in the digital domain, or all signals are summed in the analog domain to be later digitized by a single ADC. Summation in the analog domain is not straightforward and usually additional circuitry is needed, eventually resulting in higher power and area consumption. Also, the use of a number of ADCs entails higher power and area overhead.
These circuits for digitizing a sum of signals can be directly embedded in a feed-forward (FF) sigma-delta ADC, which is traditionally used in a wide variety of applications, such as instrumentation, biomedical, audio and radio.
In fact, sigma-delta modulators using multi-bit quantization with FF topologies achieve high-resolution with relatively low power dissipation. Unfortunately, the addition and quantization operations of multi-bit FF topologies face a power/resolution trade-off due to conflicting requirements on the adder and quantizer. Hence, there is an ongoing effort in implementing architectures that perform the addition while also reducing the number of comparators used in the multi-bit quantizer to further reduce the power consumption.
FIG. 1 shows an example of a standard multi-bit single-loop feed-forward ΣΔ modulator architecture. An analog adder 12 is used to perform the summation of the feed-forward paths while a flash quantizer 13 is traditionally employed for the internal multi-bit quantization. In FIG. 1 the power consumption and/or design constraints of the adder and quantizer blocks may become critical. The analog adder 12 can be implemented as an active or passive adder. On the one hand, an active adder is a power hungry solution because of the large voltage swing at its output and the large load from the flash quantizer. On the other hand, a passive adder is usually implemented as a capacitor divider that attenuates the input signal at the input of the quantizer, so comparator offset requirements become more stringent. A flash quantizer guarantees a low-latency quantization but requires high power consumption and large area (both exponentially scaling with quantizer resolution).
In feed-forward topologies the input signal Xin, and the integrator outputs (state variables) Xi (i=1 . . . L) are added at the input of the quantizer 13 through the feed-forward coefficients ci (i=1 . . . L). As aforementioned, two approaches are usually available to implement this addition, i.e. active or passive addition.
In case a passive addition is applied, the signal addition does not rely on any active circuitry. It is implemented with a switched capacitor network consisting of L switched capacitor branches as shown in FIG. 2. If Σi=1Lci the capacitors used to implement the FF coefficients are integer fractions of the capacitor Cf0:
                                          C            fi                    =                                                    c                i                            ·                              C                                  f                  ⁢                                                                          ⁢                  0                                                      =                                                                                c                    i                    *                                                        c                    T                                                  ·                                  C                                      f                    ⁢                                                                                  ⁢                    0                                                              =                                                                    c                    i                    *                                    ·                                      C                    u                                                  ⁢                                                                  ⁢                for                ⁢                                                                  ⁢                                  (                                      i                    =                                          1                      ⁢                                                                                          ⁢                      …                      ⁢                                                                                          ⁢                      L                                                        )                                                                    ⁢                                  ⁢        where                            (        1        )                                          C                      f            ⁢                                                  ⁢            0                          =                                            C              u                        ·                                          ∑                                  i                  =                  1                                L                            ⁢                                                          ⁢                              c                i                                              =                                    c              T                        ·                          C              u                                                          (        2        )            
If Σi=1Lci the capacitors Cf1 are implemented as integer multiple of the unit capacitor Cu:Cfi=ci·Cu Cfi=ci·Cu  (3)The value of Cu is determined by taking into account mismatch constraints.
The signal at the adder output is attenuated by a factor α=1+Σi=1Lci. This attenuation renders the quantizer offset requirements more stringent and, in turn, the quantizer power consumption higher. In single-bit implementations the amplitude information is not used because only the sign information is detected. In multi-bit implementations the attenuation must be compensated by a corresponding amplification a in order to re-establish signal dynamic at the quantizer input. This amplification is power consuming as it should settle fast and it should reach full scale output dynamic.
The second option is to perform the addition actively. In this approach, the addition at the quantizer input is performed using a switched capacitor configuration as shown in FIG. 3. An amplifier 30 is used in order to perform the required summing function without attenuating the final sum signal. This approach is power consuming as it requires L+1 amplifiers for an L-th order sigma-delta modulator. The output dynamic of the adder amplifier 30 should be maximized in order to relax the quantizer offset requirements.
Multi-bit quantizers used in sigma-delta modulators usually adopt flash topology requiring 2N−1 comparators, with N being the number of bits in the quantizer. As a consequence, flash quantizers result being power and area consuming.
A conventional capacitive N-bit SAR analog-to-digital converter as in FIG. 4 (showing a single ended schematic of a fully-differential implementation) employs a comparator 41, a shift register (part of the SAR control logic block 42) and a capacitive Digital-to-Analog Converter (DAC) array 40. Following a binary search algorithm, the DAC approximates the input signal. The DAC capacitor array 40 can be implemented by a binary weighted capacitor or by a split capacitor array. Typically a capacitor is associated to each bit.
The conventional SAR algorithm performed on a sample of the input analog signal follows three phases:                Sampling phase: Input signal Xin is sampled on the capacitor array. The signal SMPL is high and connects the top plate of the capacitor array to VCM.        Bit cycling: The successive approximation algorithm approximates the input signal one bit at the time from the Most Significant Bit (MSB) to the Least Significant Bit (LSB). During each cycle, the bottom plate of the capacitor associated to the bit being evaluated is first connected to the positive reference voltage VREFP. If the voltage VX is larger than the VCM, the capacitor bottom plate is maintained at VREFP. Otherwise it is connected to VREFN. At the end of this phase the analog sample is approximated by the DAC as        
      V    DAC    =            ∑              j        =        1            N        ⁢                  ⁢                  2                  (                      j            -            1                    )                    ·              D        j            ·              V        REF                            where VREF=VREFP−VREFN, Dj(=±1) is the result of the j-th comparator decision and its value represents the j-th bit.        Purging: The residual charge on the capacitor array is removed before starting a new conversion cycle.These phases are common to both synchronous and asynchronous implementation of the Successive Approximation algorithm. In feed-forward sigma-delta modulators the SAR conversion happens during the modulator sampling phase (phase f1) so that the output of the multi-bit quantizer is available for the feedback DAC during the integration phase (phase f2).        
In the paper “A 1V 350 μW 92 dB SNDR 24 kHz ΣΔ Modulator in 0.18 μm CMOS” (Liu et al., ASSCC Dig. Tech. Papers, pp. 1-4, November 2010) a high-precision multi-bit 3rd-order sigma-delta (ΣΔ) modulator optimized for audio applications is presented. A single loop ΣΔ modulator topology with input feed-forward paths and multi-bit quantizers is applied to deal with the limited power supply. The feed-forward paths are digitized by two successive approximation quantizers (SAQs) and then summed in the digital domain. Although the use of SAQs leads to a more power efficient implementation, two SAQs and a digital adder are still needed. The use of three integrators and two quantizers reduces the stability and increases power and area consumption, when compared to a multi-bit 2nd-order ΣΔ modulator with only one SAQ.
There is a need for an adder circuit suitable for use in a feed-forward sigma-delta modulator that requires a limited amount of power consumption and area. Further, there is a need for a sigma-delta modulator provided with an efficient adder circuit.